1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device which includes a plurality of memory cell blocks comprising nonvolatile semiconductor storage elements each having a floating gate electrode, and selects a memory cell block by a selection gate transistor.
2. Description of the Related Art
A memory cell of an EEPROM generally has a MISFET structure formed by stacking a floating gate electrode (charge storage layer) and control gate electrode on a semiconductor substrate. This nonvolatile memory cell transistor stores data by using the difference between a threshold value in a state in which electric charge is injected to the floating gate electrode and a threshold value in a state in which the electric charge is removed. A tunnel current acts to inject and remove the electric charge via a tunnel insulating film between the floating gate electrode and a substrate channel.
An EEPROM having a NAND cell unit formed by connecting a plurality of memory cells in series is a so-called NAND EEPROM. The NAND EEPROM can increase the memory density because the number of selection transistors is smaller than that of an EEPROM in which each memory cell has a selection gate.
A flash memory erases data by allowing a tunnel current to flow via a tunnel insulating film between a floating gate electrode and substrate channel, so as not to be readily influenced by the short channel effect during data erase. For example, this erase is executed in a plurality of memory cells at the same time in order to increase the number of memory cells to be erased per unit time. Therefore, electrons are extracted from the floating gate electrode to the substrate by applying a positive voltage of 10 V or more, e.g., 20 V to a semiconductor memory cell well in which memory cells are formed.
On the other hand, data write is performed by holding the semiconductor well voltage at zero, and applying a positive voltage of 10 V or more to the source/drain diffusion layers of the memory cell having a charge/discharge capacity smaller than that of the semiconductor well. This makes it possible to reduce the electric power for charging/discharging the well, and increase the operating speed.
To avoid imperfect data write in, e.g., NAND-connected memory cells, it is necessary to adequately decrease the variations in threshold value of unselected memory cells connected in series with a selected memory cell, thereby reducing current variations when data is read out from the selected memory cell. To maintain a narrow threshold value distribution after data write and reduce chip variations, the positive voltage described above must be controlled within the variation range of, e.g., 0.5 V or less. Accordingly, a large leakage current or low breakdown voltage of the control gate electrode or a large threshold value variation causes imperfect data write.
Note that as a related technique of this type, a technique pertaining to an isolation in a NAND flash memory is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 2005-79165).